Design Techniques and Modeling for 60GHz Applications With a 65nm-CMOS-RF Technology

TitleDesign Techniques and Modeling for 60GHz Applications With a 65nm-CMOS-RF Technology
Publication TypeConference Paper
Year of Publication2008
AuthorsAloui S, Kerherve E, Belot D, Plana R
Conference NameMillimeter Waves, 2008. GSMM 2008. Global Symposium on
Date Publishedapril
KeywordsCMOS integrated circuits, CMOS-RF technology, compact inductor, distributed elements, frequency 60 GHz, inductors, integrated circuit design, interconnect lines, lumped elements, millimeter CMOS power amplifier, millimetre wave amplifiers, millimetre wave integrated circuits, power amplifiers, resistive parasitic, size 65 nm, STMicroelectronics
Abstract

To exploit the unlicensed band at frequencies around 60 GHz, a certain number of design rules is considered. This paper highlights the difficulties to design a millimeter CMOS power amplifier (PA). A model of a compact inductor and interconnect lines is detailed. This model takes into account substrate and resistive parasitic. A 65 nm CMOS technology from STMicroelectronics has been used. Innovative techniques are implemented in the design of a power amplifier (PA) which is optimized to deliver the maximum linear output power. To obtain good performances in a small surface of silicon, it has been designed, with both lumped and distributed elements. The PA delivers a linear output power of 8.9 dBm with just an area of 0.48 mm*0.6 mm including pads.

DOI10.1109/GSMM.2008.4534611