A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications

TitleA 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications
Publication TypeConference Paper
Year of Publication2011
AuthorsOsorio JF, Vaucher CS, Huff B, v.d. Heijden E, de Graauw A
Conference NameSolid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Date Publishedfeb.
Keywords3G mobile communication, 3G-LTE base-station networks, CMOS digital integrated circuits, CMOS process, divider-by-two circuit, field effect MIMIC, frequency 21.7 GHz to 27.8 GHz, frequency dividers, frequency multiplier-by-two circuit, frequency multipliers, frequency synthesizer, frequency synthesizers, IEEE 802.15.3c communication standard, Long Term Evolution, microwave links, mm-wave communication application, multiplying circuits, personal area networks, phase locked loops, PLL, power dissipation, residual phase modulation, size 45 nm, sliding-IF configuration
Abstract

This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57 #x00B0;rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.

DOI10.1109/ISSCC.2011.5746317