A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

TitleA 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications
Publication TypeConference Paper
Year of Publication2010
AuthorsRichard O, Siligaris A, Badets F, Dehos C, Dufis C, Busson P, Vincent P, Belot D, Urard P
Conference NameSolid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Date Publishedfeb.
KeywordsCMOS integrated circuits, CMOS technology, field effect MIMIC, frequency 17.5 GHz to 20.94 GHz, frequency 35 GHz to 41.88 GHz, frequency synthesizer, frequency synthesizers, phase locked loops, PLL, power 80 mW, push-push quadrature VCO, size 65 nm, voltage-controlled oscillators, wireless HD applications
Abstract

A complete frequency synthesizer occupying 1.1 mm2 in 65 nm CMOS is presented. It is composed of a push-push quadrature VCO that delivers two L0 signals in 20 and 40 GHz bands. The PLL consumes 80 mW including buffers, and achieves a phase noise lower than -100 and -97.5 dBc/Hz for the 20 GHz and the 40 GHz signals, respectively.

DOI10.1109/ISSCC.2010.5433941